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tmeissner
/
cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
131
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
8d0430ac03
cryptocores
/
des
/
sim
/
vhdl
History
T. Meissner
e9cd57264b
changed option 'T' to 'S'
11 years ago
..
makefile
changed option 'T' to 'S'
11 years ago
tb_des.tcl
moved vhdl testbench files into separate directory vhdl under sim
13 years ago
tb_des.vhd
moved vhdl testbench files into separate directory vhdl under sim
13 years ago