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tmeissner
/
cryptocores
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Activity
cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
134
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
a89d5ba3d8
cryptocores
/
cbctdes
/
sim
History
T. Meissner
f8226943a3
changed reset & clk timing according to vhdl testbench
11 years ago
..
verilog
changed reset & clk timing according to vhdl testbench
11 years ago
vhdl
adapted paths
11 years ago