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tmeissner
/
cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
162
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
af8fe6023d
cryptocores
/
tdes
/
sim
History
T. Meissner
1d858ce952
added removing of tb_tdes binary and *.o files in clean target
11 years ago
..
verilog
added wait for disactivated reset before running testcases
11 years ago
vhdl
added removing of tb_tdes binary and *.o files in clean target
11 years ago