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176 lines
5.4 KiB
176 lines
5.4 KiB
-- ======================================================================
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-- AES encryption/decryption
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-- Copyright (C) 2019 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.aes_pkg.all;
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entity aes_enc is
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generic (
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design_type : string := "ITER"
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);
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port (
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reset_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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key_i : in std_logic_vector(0 to 127); -- key input
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data_i : in std_logic_vector(0 to 127); -- data input
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valid_i : in std_logic; -- input key/data valid flag
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accept_o : out std_logic;
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data_o : out std_logic_vector(0 to 127); -- data output
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valid_o : out std_logic; -- output data valid flag
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accept_i : in std_logic
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);
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end entity aes_enc;
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architecture rtl of aes_enc is
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-- Fixed round keys for verification until key schedule is implemented
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type t_key_array is array (1 to 11) of t_key;
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constant c_round_keys : t_key_array := (
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(x"2b7e1516", x"28aed2a6", x"abf71588", x"09cf4f3c"),
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(x"a0fafe17", x"88542cb1", x"23a33939", x"2a6c7605"),
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(x"f2c295f2", x"7a96b943", x"5935807a", x"7359f67f"),
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(x"3d80477d", x"4716fe3e", x"1e237e44", x"6d7a883b"),
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(x"ef44a541", x"a8525b7f", x"b671253b", x"db0bad00"),
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(x"d4d1c6f8", x"7c839d87", x"caf2b8bc", x"11f915bc"),
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(x"6d88a37a", x"110b3efd", x"dbf98641", x"ca0093fd"),
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(x"4e54f70e", x"5f5fc9f3", x"84a64fb2", x"4ea6dc4f"),
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(x"ead27321", x"b58dbad2", x"312bf560", x"7f8d292f"),
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(x"ac7766f3", x"19fadc21", x"28d12941", x"575c006e"),
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(x"d014f9a8", x"c9ee2589", x"e13f0cc8", x"b6630ca6")
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);
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signal s_round_key : t_key := (others => (others => '0'));
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begin
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-- psl default clock is rising_edge(Clk_i);
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IterG : if design_type = "ITER" generate
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signal s_round : t_enc_rounds;
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begin
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s_round_key <= c_round_keys(s_round) when s_round >= 1 and s_round <= 11 else
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(others => (others => '0'));
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CryptP : process (reset_i, clk_i) is
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variable v_state : t_datatable2d;
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begin
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if (reset_i = '0') then
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v_state := (others => (others => (others => '0')));
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s_round <= 0;
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accept_o <= '0';
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data_o <= (others => '0');
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valid_o <= '0';
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elsif (rising_edge(clk_i)) then
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case s_round is
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when 0 =>
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accept_o <= '1';
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if (accept_o = '1' and valid_i = '1') then
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accept_o <= '0';
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v_state := set_state(data_i);
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s_round <= s_round + 1;
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end if;
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when 1 =>
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v_state := addroundkey(v_state, s_round_key);
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s_round <= s_round + 1;
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when t_enc_rounds'high-1 =>
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v_state := subbytes(v_state);
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v_state := shiftrow(v_state);
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v_state := addroundkey(v_state, s_round_key);
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s_round <= s_round + 1;
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-- set data & valid to save one cycle
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valid_o <= '1';
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data_o <= get_state(v_state);
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when t_enc_rounds'high =>
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if (valid_o = '1' and accept_i = '1') then
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valid_o <= '0';
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data_o <= (others => '0');
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s_round <= 0;
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-- Set accept to save one cycle
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accept_o <= '1';
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end if;
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when others =>
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v_state := subbytes(v_state);
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v_state := shiftrow(v_state);
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v_state := mixcolumns(v_state);
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v_state := addroundkey(v_state, s_round_key);
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s_round <= s_round + 1;
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end case;
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end if;
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end process CryptP;
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-- synthesis off
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verification : block is
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signal s_data : std_logic_vector(0 to 127);
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begin
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s_data <= data_o when rising_edge(clk_i) else
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128x"0" when reset_i = '0';
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-- psl cover accept_o;
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-- psl assert always (accept_o -> s_round = 0);
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-- psl cover valid_i and accept_o;
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-- psl assert always (valid_i and accept_o -> next not accept_o);
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-- psl cover valid_o;
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-- psl assert always (valid_o -> s_round = t_enc_rounds'high);
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-- psl cover valid_o and accept_i;
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-- psl assert always (valid_o and accept_i -> next not valid_o);
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-- psl cover valid_o and not accept_i;
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-- psl assert always (valid_o and not accept_i -> next valid_o);
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-- psl assert always (valid_o and not accept_i -> next data_o = s_data);
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end block verification;
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-- synthesis on
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end generate IterG;
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end architecture rtl;
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