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tmeissner
/
cryptocores
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Activity
cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
218
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
b602931174
cryptocores
/
cbcmac_des
/
sim
History
T. Meissner
313a08b6f3
add verilog simulation environment for cbcmac-des
10 years ago
..
verilog
add verilog simulation environment for cbcmac-des
10 years ago
vhdl
add implementation & testbench of CBCMAC with DES algorithm
10 years ago