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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdlghdlosvvmfpgatestbenchesverilogcryptography
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167 Commits
1 Branch
1.7 MiB
VHDL 51.3%
Verilog 33.4%
Makefile 10.2%
C 3.5%
Tcl 1.5%
 
 
 
 
 
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cryptocores/des/sim/verilog
History
T. Meissner 734efbc59f added test cases for decryption in stimuli & checker; bugfix wwith validout detection 12 years ago
..
data_input.txt added test data for decryption test cases 12 years ago
data_output.txt added test data for decryption test cases 12 years ago
key_input.txt added test data for decryption test cases 12 years ago
makefile dependency files now moved into 2 variables SRC_FILES & SIM_FILES 12 years ago
tb_des.tcl removed 'outdex' reg from waveform viewer 12 years ago
tb_des.v added test cases for decryption in stimuli & checker; bugfix wwith validout detection 12 years ago
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