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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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128
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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f8226943a3
master
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cryptocores
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tdes
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sim
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vhdl
History
T. Meissner
dd979b5cd3
adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources
12 years ago
..
makefile
adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources
12 years ago
tb_tdes.tcl
moved into seperate vhdl folder
12 years ago
tb_tdes.vhd
beauty care
12 years ago