Trying to verify Verilog/VHDL designs with formal methods and tools
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  1. DUT := fwft_fifo
  2. SRC := ../fifo/fifo.vhd ${DUT}.vhd
  3. .PHONY: cover bmc prove synth all clean
  4. all: cover bmc prove
  5. cover bmc prove: ${DUT}.vhd symbiyosys.sby
  6. sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
  7. ${DUT}_synth.vhd: ${SRC}
  8. ghdl --synth --std=08 --no-formal -gDepth=16 -gWidth=16 ${SRC} -e ${DUT} > $@
  9. synth: ${DUT}.json
  10. ${DUT}.json: ${DUT}_synth.vhd
  11. yosys -m ghdl -p 'ghdl --std=08 --no-formal -gDepth=16 -gWidth=16 ${SRC} -e ${DUT}; synth_ice40 -top ${DUT} -json $@'
  12. clean:
  13. rm -rf work ${DUT}.json ${DUT}_synth.vhd