tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Adapt to use GHDL as plugin for Yosys VHDL synthesis

5 years ago

Add simple VAI register file as base to try to formal verify FSM designs

6 years ago

vai_reg: vai_reg.vhd symbiyosys.sby
	sby --yosys "yosys -m ghdl" -f -d work symbiyosys.sby


clean:
	rm -rf work