tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - vai_reg/Makefile at 195765a2aa640ba46ea9989e10e204d2b5de637e - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								vai_reg: vai_reg.vhd symbiyosys.sby
 									sby --yosys "yosys -m ghdl" -f -d work symbiyosys.sby
 								clean:
 									rm -rf work