tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Remove gitignore from alu folder; added link to Yosys

6 years ago

6 years ago

Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv

6 years ago

alu: alu.vhd alu_t.sv alu_f.sby
	sby -f -d work alu_f.sby


clean:
	rm -rf work