tmeissner
/
formal_hw_verification
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 6 Wiki Activity
Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
2 Commits
3 Branches
324 KiB
Tree: 2f7959db61
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '2f7959db61'
${ noResults }
formal_hw_verification/alu/Makefile

2 lines
58 B
Raw Normal View History

Remove gitignore from alu folder; added link to Yosys
6 years ago
Inital commit
6 years ago
 
  1. alu: alu.vhd alu_t.sv alu_f.sby
  2. 	sby -f -d work alu_f.sby