Browse Source

Removing verific related dlatchsr from master branch

T. Meissner 1 month ago
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commit
903931b2d9
5 changed files with 0 additions and 105 deletions
  1. 0
    3
      README.md
  2. 0
    7
      dlatchsr/Makefile
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    42
      dlatchsr/dlatch.vhd
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    17
      dlatchsr/dlatch_f.sby
  5. 0
    36
      dlatchsr/dlatch_t.sv

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README.md View File

@@ -17,8 +17,5 @@ A simple ALU design in VHDL. The formal checks contain various simple properties
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 ### counter
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 A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.
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-### dlatch
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-A simple test design which generates the `Unsupported cell type $dlatchsr` error using with Verific plugin (verific branch).
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-
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 ### vai_reg
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 A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.

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dlatchsr/Makefile View File

@@ -1,7 +0,0 @@
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-.PHONY: dlatch
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-dlatch: dlatch.vhd dlatch_t.sv dlatch_f.sby
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-	sby -f -d work dlatch_f.sby
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-
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-.PHONY: clean
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-clean:
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-	rm -rf work

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dlatchsr/dlatch.vhd View File

@@ -1,42 +0,0 @@
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-library ieee;
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-use ieee.std_logic_1164.all;
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-use ieee.numeric_std.all;
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-
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-
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-
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-entity dlatch is
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-  generic (
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-    Init : std_logic_vector(31 downto 0) := x"DEADBEEF"
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-  );
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-  port (
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-    Reset_n_i : in  std_logic;
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-    Clk_i     : in  std_logic;
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-    Wen_i     : in  std_logic;
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-    Data_i    : in  std_logic_vector(15 downto 0);
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-    Data_o    : out std_logic_vector(31 downto 0)
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-  );
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-end entity dlatch;
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-
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-
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-
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-architecture rtl of dlatch is
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-
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-
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-begin
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-
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-
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-  process (Reset_n_i, Clk_i) is
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-  begin
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-    if (Reset_n_i = '0') then
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-      Data_o <= Init;
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-    elsif (rising_edge(Clk_i)) then
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-      if (Wen_i = '1') then
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-        Data_o(7 downto 0) <= Data_i(7 downto 0);
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-	Data_o(23 downto 16) <= Data_i(15 downto 8);
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-      end if;
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-    end if;
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-  end process;
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-
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-
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-end architecture rtl;
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-

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dlatchsr/dlatch_f.sby View File

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-[options]
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-mode prove
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-depth 20
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-# falis with multiclock disabled
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-multiclock off
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-
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-[engines]
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-smtbmc
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-
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-[script]
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-verific -vhdl dlatch.vhd
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-verific -formal dlatch_t.sv
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-prep -top dlatch_t
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-
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-[files]
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-dlatch.vhd
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-dlatch_t.sv

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dlatchsr/dlatch_t.sv View File

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-module dlatch_t (
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-    input         Reset_n_i,
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-    input         Clk_i,
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-    input         Wen_i,
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-    input  [15:0] Data_i,
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-    output [31:0] Data_o
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-);
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-
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-
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-  `define INIT_VALUE 32'hDEADBEEF
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-
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-
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-  dlatch #(.Init(`INIT_VALUE)) dlatch_i (
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-    .Reset_n_i(Reset_n_i),
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-    .Clk_i(Clk_i),
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-    .Wen_i(Wen_i),
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-    .Data_i(Data_i),
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-    .Data_o(Data_o)
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-  );
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-
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-
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-  reg init_state = 1;
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-
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-  always @(*)
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-    if (init_state) assume (!Reset_n_i);
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-
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-  always @(posedge Clk_i)
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-    init_state = 0;
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-
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-
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-  always @(*)
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-    if (!Reset_n_i) assert (Data_o == `INIT_VALUE);
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-
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-
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-endmodule
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-