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Add infos about fifo model to README

T. Meissner 1 month ago
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@@ -17,5 +17,8 @@ A simple ALU design in VHDL. The formal checks contain various simple properties
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 ### counter
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 A simple counter design in VHDL. The testbench contains various simple properties used by assert & cover directives which are proved with the SymbiYosys tool.
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+### fifo
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+A simple synchronous FIFO with various checks for write/read pointers, data and flags.
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 ### vai_reg
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 A simple register file with VAI (valid-accept-interface) which serves as test design to try formal verification of FSMs.