formal_hw_verification

324 KiB

Branch: master

Author	SHA1	Message	Date
T. Meissner	3d57fff226	Replace reset checks by async VHDL asserts; Add assumptions about inputs	3 years ago
T. Meissner	d94585cad8	Making counter design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module when using generics * Add some simple PSL assertions	4 years ago
T. Meissner	3e621b02e9	Add alu checks * Add asserts for correct behaviour of Overflow flag * Switch to smtbmc engine in prove mode (much faster than abc)	4 years ago
T. Meissner	d420b00310	Making alu design work with GHDL synthesis * Remove unused SVA properties file * Makefile optimizations * Use prep auto-top option to prevent error with not founded top-level module * Rewrite assignments of Dout_o & Overflow_o as GHDL synthesis don't support concatenation on left side of assignments * Add some simple PSL assertions	4 years ago
T. Meissner	6c3a6db83b	Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module	4 years ago
T. Meissner	367343cff5	Add make targets and SymbiYosys tasks for cover, bmc & prove	5 years ago
T. Meissner	195765a2aa	Adapt to use GHDL as plugin for Yosys VHDL synthesis	5 years ago
T. Meissner	38ae7057c2	Incomment proof with abc pdr	5 years ago
T. Meissner	a0f6a0b81d	Add simple VAI register file as base to try to formal verify FSM designs	5 years ago