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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter
T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 3 years ago
..
Makefile Making counter design work with GHDL synthesis 4 years ago
counter.vhd Replace reset checks by async VHDL asserts; Add assumptions about inputs 3 years ago
symbiyosys.sby Replace reset checks by async VHDL asserts; Add assumptions about inputs 3 years ago