Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys
T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 3 months ago
..
Makefile parameterize design; fix minor makefile problemswq 5 months ago
counter.vhd Add genric setting counter end value 4 months ago
counter_f.sby Add clock constrain using global clocking 4 months ago
counter_t.sv Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 3 months ago