Trying to verify Verilog/VHDL designs with formal methods and tools
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T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 10 months ago
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Makefile Making counter design work with GHDL synthesis 2 years ago
counter.vhd Replace reset checks by async VHDL asserts; Add assumptions about inputs 10 months ago
symbiyosys.sby Replace reset checks by async VHDL asserts; Add assumptions about inputs 10 months ago