Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys
T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 1 month ago
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Makefile parameterize design; fix minor makefile problemswq 3 months ago
counter.vhd Add genric setting counter end value 2 months ago
counter_f.sby Add clock constrain using global clocking 2 months ago
counter_t.sv Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 1 month ago