Trying to verify Verilog/VHDL designs with formal methods and tools
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DUT := counter
.PHONY: cover bmc prove all clean
all: cover bmc prove
cover bmc prove: ${DUT}.vhd symbiyosys.sby
sby --yosys "yosys -m ghdl" -f -d work/${DUT}-$@ symbiyosys.sby $@
clean:
rm -rf work