Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys

Makefile 103B

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  1. vai_reg: vai_reg.vhd properties.sv symbiyosys.sby
  2. sby -f -d work symbiyosys.sby
  3. clean:
  4. rm -rf work