Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys
T. Meissner 38ae7057c2 Incomment proof with abc pdr 3 months ago
..
Makefile Add simple VAI register file as base to try to formal verify FSM designs 3 months ago
properties.sv Replace integer coded FSM states by symbolic state names 3 months ago
symbiyosys.sby Incomment proof with abc pdr 3 months ago
trace.gtkw Add some more signals to trace 3 months ago
vai_reg.vhd Simplify signal generation 3 months ago