Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
assertions
formal
yosys
systemverilog
sva
T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 3 months ago
..
doc Add png versions of read/write waveform examples 1 year ago
Makefile Symplifing Makefile targets 6 months ago
symbiyosys.sby Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 7 months ago
trace.gtkw Add some more signals to trace 1 year ago
vai_reg.vhd Use PSL functions instead of workarounds; add forgotten always to asserts in alu 3 months ago