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formal_hw_verification
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21 Commits (master)

Author SHA1 Message Date
  T. Meissner 3d57fff226 Replace reset checks by async VHDL asserts; Add assumptions about inputs 4 years ago
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 5 years ago
  T. Meissner bc59bfd47c Symplifing Makefile targets 5 years ago
  T. Meissner 6c3a6db83b Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 5 years ago
  T. Meissner bd5fcbcb7a GHDL supports memory with resets, finally 5 years ago
  T. Meissner e71b70d34e Add Assumptions about job req VAI interface 5 years ago
  T. Meissner 8cf0be6e4c Add many new asserts & covers 5 years ago
  T. Meissner 367343cff5 Add make targets and SymbiYosys tasks for cover, bmc & prove 5 years ago
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 5 years ago
  T. Meissner c6cc9203d3 Add png versions of read/write waveform examples 6 years ago
  T. Meissner 8586d8a265 Add frame diagrams for write/read req/acks 6 years ago
  T. Meissner 2a090443ef Add waveforms of read/write examples 6 years ago
  T. Meissner 38ae7057c2 Incomment proof with abc pdr 6 years ago
  T. Meissner 9cb4b7d291 Replace integer coded FSM states by symbolic state names 6 years ago
  T. Meissner 8edb03c011 Add a bunch of new properties; name all assert directives 6 years ago
  T. Meissner 60e2c0f301 Add some more signals to trace 6 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 6 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 6 years ago
  T. Meissner 1deb6e9789 Add vai_reg to README; using SVA default clocking 6 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 6 years ago