Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys

symbiyosys.sby 231B

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  1. [options]
  2. depth 30
  3. wait on
  4. mode prove
  5. #mode bmc
  6. [engines]
  7. smtbmc
  8. abc pdr
  9. [script]
  10. verific -vhdl vai_reg.vhd
  11. verific -formal properties.sv
  12. verific -import -extnets -all vai_reg
  13. prep -top vai_reg
  14. [files]
  15. vai_reg.vhd
  16. properties.sv