Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys

read_example.json 895B

1234567891011121314151617181920212223
  1. {signal: [
  2. {name: 'Reset_n_i', wave: '01..........'},
  3. {name: 'Clk_i', wave: 'p...........'},
  4. {},
  5. {name: 's_fsm_state', wave: '2.2.22.2.2.2', data: ['IDLE', 'GET_HEADER', 'GET_DATA', 'SEND_HEADER', 'SEND_DATA', 'SEND_FOOTER', 'IDLE']},
  6. {},
  7. {name: 'Din_i', wave: 'x..3x.......', data: ['header']},
  8. {name: 'DinStart_i', wave: '0..10.......'},
  9. {name: 'DinStop_i', wave: '0..10.......'},
  10. {name: 'DinValid_i', wave: '0..10.......'},
  11. {name: 'DinAccept_o', wave: '0.1.0.......'},
  12. {},
  13. {name: 'Dout_o', wave: 'x....3.4.5.x', data: ['header', 'data', 'footer']},
  14. {name: 'DoutStart_o', wave: '0....1.0....'},
  15. {name: 'DoutStop_o', wave: '0........1.0'},
  16. {name: 'DoutValid_o', wave: '0....1.....0'},
  17. {name: 'DoutAccept_i', wave: '0.....101010'},
  18. ],
  19. config: { hscale: 2 },
  20. head:{
  21. text:['tspan', {class:'h3'}, 'Read example (opcode 0x0)']
  22. }
  23. }