Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
systemverilog
sva
assertions
formal
yosys

write_example.json 857B

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  1. {signal: [
  2. {name: 'Reset_n_i', wave: '01........'},
  3. {name: 'Clk_i', wave: 'p.........'},
  4. {},
  5. {name: 's_fsm_state', wave: '2.2.22.2.2', data: ['IDLE', 'GET_HEADER', 'SET_DATA', 'SEND_HEADER', 'SEND_FOOTER', 'IDLE']},
  6. {},
  7. {name: 'Din_i', wave: 'x..34x....', data: ['header', 'data']},
  8. {name: 'DinStart_i', wave: '0..10.....'},
  9. {name: 'DinStop_i', wave: '0...10....'},
  10. {name: 'DinValid_i', wave: '0..1.0....'},
  11. {name: 'DinAccept_o', wave: '0.1..0....'},
  12. {},
  13. {name: 'Dout_o', wave: 'x....3.4.x', data: ['header', 'footer']},
  14. {name: 'DoutStart_o', wave: '0....1.0..'},
  15. {name: 'DoutStop_o', wave: '0......1.0'},
  16. {name: 'DoutValid_o', wave: '0....1...0'},
  17. {name: 'DoutAccept_i', wave: '0.....1010'},
  18. ],
  19. config: { hscale: 2 },
  20. head:{
  21. text:['tspan', {class:'h3'}, 'Write example (opcode 0x1)']
  22. }
  23. }