Trying to verify Verilog/VHDL designs with formal methods and tools
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18 lines
173 B

[options]
depth 30
wait on
mode prove
#mode bmc
[engines]
smtbmc
abc pdr
[script]
verific -vhdl alu.vhd
verific -formal alu_t.sv
prep -top alu_t
[files]
alu.vhd
alu_t.sv