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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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Branch: verific_problem
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formal_hw_verification/alu/alu_f.sby

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Inital commit
6 years ago
Data in/put width now unconstrained
6 years ago
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Inital commit
6 years ago
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Data in/put width now unconstrained
6 years ago
Inital commit
6 years ago
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  1. [options]
  2. depth 30
  3. wait on
  4. mode prove
  5. #mode bmc
  6. 

  7. [engines]
  8. smtbmc
  9. abc pdr
  10. 

  11. [script]
  12. verific -vhdl alu.vhd
  13. verific -formal alu_t.sv
  14. prep -top alu_t
  15. 

  16. [files]
  17. alu.vhd
  18. alu_t.sv