Trying to verify Verilog/VHDL designs with formal methods and tools
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22 lines
259 B

[tasks]
cover
bmc
prove
[options]
depth 20
cover: mode cover
bmc: mode bmc
prove: mode prove
[engines]
cover: smtbmc z3
bmc: abc bmc3
prove: abc pdr
[script]
ghdl --std=08 -gFormal=true -gDepth=8 -gWidth=4 fifo.vhd -e fifo
prep -auto-top
[files]
fifo.vhd