tmeissner/formal_hw_verification - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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Add simple FIFO model incl. formal tests

4 years ago

Add data flow checks in fifo units

4 years ago

Add simple FIFO model incl. formal tests

4 years ago

fifo: Add example for GHDL property replication * By replacing the goto operator with non-literal parameter by counting the read enabled with simple VHDL counters we can now replicate the properties instead of writing them all out. * Decrease the data width to decrease run-time of unbounded proofs

3 years ago

Add simple FIFO model incl. formal tests

4 years ago

[tasks]
cover
bmc
prove

[options]
depth 20
cover: mode cover
bmc: mode bmc
prove: mode prove

[engines]
cover: smtbmc z3
bmc: abc bmc3
prove: abc pdr

[script]
ghdl --std=08 -gFormal=true -gDepth=8 -gWidth=4 fifo.vhd -e fifo
prep -auto-top

[files]
fifo.vhd