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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/alu
T. Meissner ac767bb9d3 Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 years ago
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Makefile Makefile: add clean target; fixed Reset_n_i port dir in alu_t.sv 6 years ago
alu.vhd Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 years ago
alu_f.sby Data in/put width now unconstrained 6 years ago
alu_t.sv Use SVA defaults for clock & reset; minor RTL optimizations for bettrer readability 6 years ago