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  1. `timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
  2. // simplified CC_PLL model
  3. module CC_PLL #(
  4. parameter REF_CLK = "", // e.g. "10.0"
  5. parameter OUT_CLK = "", // e.g. "50.0"
  6. parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
  7. parameter LOW_JITTER = 1,
  8. parameter CI_FILTER_CONST = 2,
  9. parameter CP_FILTER_CONST = 4
  10. )(
  11. input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
  12. input USR_LOCKED_STDY_RST, USR_SET_SEL,
  13. output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
  14. output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
  15. );
  16. reg r_pll_clk;
  17. reg r_user_pll_locked;
  18. // OUT_FREQ = 1 MHz
  19. integer clk_half_period = 50;
  20. initial begin
  21. r_pll_clk = 1'b0;
  22. r_user_pll_locked = 1'b1;
  23. end
  24. always #clk_half_period r_pll_clk = ~r_pll_clk;
  25. assign CLK0 = r_pll_clk;
  26. assign USR_PLL_LOCKED = r_user_pll_locked;
  27. endmodule
  28. // simplified CC_CFG_END model
  29. module CC_CFG_END (
  30. output CFG_END
  31. );
  32. assign CFG_END = 1'b1;
  33. endmodule
  34. module tb_uart_reg;
  35. // DUT in/out
  36. reg clk = 1'b0;
  37. reg rst_n = 1'b1;
  38. reg uart_rx;
  39. wire uart_tx;
  40. // Testbench variables
  41. reg [7:0] tx_data = 8'h0;
  42. reg [7:0] rx_data = 8'h0;
  43. // Testbench 1/2 clock period
  44. localparam clk_half_period = 50;
  45. // UART period calculation (9600 baud)
  46. localparam uart_bit_period = 1000000000 / 9600;
  47. localparam uart_bit_half_period = uart_bit_period/2;
  48. uart_reg UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_rx_i(uart_rx), .uart_tx_o(uart_tx));
  49. // set dumpfile
  50. initial begin
  51. $dumpfile ("tb_uart_reg.fst");
  52. $dumpvars (0, tb_uart_reg);
  53. end
  54. // Setup simulation
  55. initial begin
  56. uart_rx = 1'b1;
  57. #1 rst_n = 1'b0;
  58. #120 rst_n = 1'b1;
  59. end
  60. // Generate 10 mhz clock
  61. always #clk_half_period clk = !clk;
  62. // Stimuli generator
  63. initial
  64. forever @(posedge rst_n) begin
  65. uart_rx = 1'b1;
  66. #uart_bit_period;
  67. for (integer tx = 0; tx < 32; tx = tx + 1) begin
  68. tx_data = tx;
  69. $display ("UART send: 0x%h", tx_data);
  70. uart_rx = 1'b0;
  71. #uart_bit_period;
  72. for (integer i = 0; i <= 7; i = i + 1) begin
  73. uart_rx = tx_data[i];
  74. #uart_bit_period;
  75. end
  76. uart_rx = 1'b1;
  77. #uart_bit_period;
  78. #uart_bit_period
  79. #uart_bit_period;
  80. end
  81. end
  82. // Checker
  83. initial begin
  84. @(posedge rst_n)
  85. for (reg [7:0] rx = 0; rx < 32; rx = rx + 1) begin
  86. @(negedge uart_tx)
  87. #uart_bit_period;
  88. #uart_bit_half_period;
  89. for (integer i = 0; i <= 7; i = i + 1) begin
  90. rx_data[i] = uart_tx;
  91. #uart_bit_period;
  92. end
  93. assert (rx_data == rx)
  94. $display("UART recv: 0x%h", rx_data);
  95. else
  96. $warning("UART receive error, got 0x%h, expected 0x%h", rx_data, rx);
  97. end
  98. $display ("UART tests finished");
  99. $finish;
  100. end
  101. endmodule