Add PnR pass and constraint file

blink/rtl/blink.vhd

@@ -33,21 +33,21 @@ begin
   pll : CC_PLL
   generic map (
     REF_CLK => "10",
-    OUT_CLK => "1",
+    OUT_CLK => "30",
     PERF_MD => "SPEED"
   )
   port map (
     CLK_REF             => clk_i,
     CLK_FEEDBACK        => '0',
     USR_CLK_REF         => '0',
-    USR_LOCKED_STDY_RST => not rst_n_i,
+    USR_LOCKED_STDY_RST => '0',
     USR_PLL_LOCKED_STDY => open,
     USR_PLL_LOCKED      => s_pll_lock,
     CLK270              => open,
     CLK180              => open,
-    CLK0                => open,
+    CLK0                => s_pll_clk,
     CLK90               => open,
-    CLK_REF_OUT         => s_pll_clk
+    CLK_REF_OUT         => open
   );
 
   process (s_pll_clk, rst_n_i) is

blink/syn/Makefile

@@ -2,21 +2,32 @@ DESIGN_NAME := blink
 WORK_FILES   := ../rtl/blink.vhd
 GM_FILES    := ../../lib/components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
+YOSYSPIPE   := -nomx8 -luttree -retime
+PNRFLAGS    := -sp off -om 3 -cdf off -pin off -plc off -cCP on
+PNRTOOL     := $(shell which p_r)
 
-.PHONY: all syn
+.PHONY: all syn imp
 
-all: syn
+all: imp
 syn: ${DESIGN_NAME}.v
+imp: ${DESIGN_NAME}.bit
 
-work-obj08.cf: ${WORK_FILES} gatemate-obj08.cf
+build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf
 	ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
 
-gatemate-obj08.cf: ${GM_FILES}
+build/gatemate-obj08.cf: ${GM_FILES}
 	mkdir -p build
 	ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
 
-${DESIGN_NAME}.v: work-obj08.cf
-	yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -nomx8 -vlog $@' 2>&1 | tee build/yosys-report.txt
+${DESIGN_NAME}.v: build/work-obj08.cf
+	yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
+	  2>&1 | tee build/yosys-report.txt
+
+${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
+	cd build && \
+	  ${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
+	  2>&1 | tee p_r-report.txt && \
+	  mv ${DESIGN_NAME}*.bit ../$@
 
 clean :
 	echo "# Cleaning files"

blink/syn/blink.ccf

@@ -0,0 +1,13 @@
+# Configuration for the Gatemate eval board
+
+Pin_in   "clk_i"   Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
+Pin_in   "rst_n_i" Loc = "IO_EB_B0"; # SW3
+
+Pin_out  "led_n_o[0]"  Loc = "IO_EB_B1"; # LED D1
+Pin_out  "led_n_o[1]"  Loc = "IO_EB_B2"; # LED D2
+Pin_out  "led_n_o[2]"  Loc = "IO_EB_B3"; # LED D3
+Pin_out  "led_n_o[3]"  Loc = "IO_EB_B4"; # LED D4
+Pin_out  "led_n_o[4]"  Loc = "IO_EB_B5"; # LED D5
+Pin_out  "led_n_o[5]"  Loc = "IO_EB_B6"; # LED D6
+Pin_out  "led_n_o[6]"  Loc = "IO_EB_B7"; # LED D7
+Pin_out  "led_n_o[7]"  Loc = "IO_EB_B8"; # LED D8