tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
42 Commits
2 Branches
209 KiB
Tree: 1777fbd742
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '1777fbd742'
${ noResults }
Commit Graph

3 Commits (1777fbd742d6166b56b84f4a369ec441a6a0f419)

Author SHA1 Message Date
  T. Meissner 0df7a047be Add uart_trng design 4 years ago
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 4 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 4 years ago