gatemate_experiments

37 Commits

2 Branches

209 KiB

Commit Graph

Author	SHA1	Message	Date
T. Meissner	32fa71a90b	Increase pll clock to 10 MHz, add uart_loop design to readme	2 years ago
T. Meissner	8cf0e6185c	blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code	2 years ago
T. Meissner	61affc8b49	Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations	2 years ago

Author

SHA1

Message

Date

T. Meissner

32fa71a90b

Increase pll clock to 10 MHz, add uart_loop design to readme

2 years ago

T. Meissner

8cf0e6185c

blink & uart_reg designs are working now

* Yosys with -luttree option seems to generate Verilog
  netlist which GateMate p_r tool cannot handle correctly
* If -luttree option is used you get bitfiles with nearly
  random behaviour
* So, the Yosys -luttree option is removed to get correctly
  working designs, even that the GateMate documentation recommends
  to use the option
* Result is a design with worse timing, but it's working as
  desired :)

* Add targets to run post-synthesis & post-implementation simulations
* Add Verilog test benches for post-syn/post-imp simulations
* Remove debug code

2 years ago

T. Meissner

61affc8b49

Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations

2 years ago

3 Commits (194f4c78e00ef0a11010495c561f6c9f4e7d4f23)