2 Commits (32fa71a90b5ed32d2064a3eafb58f5beb0ab8c18)

Author SHA1 Message Date
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 3 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 3 years ago
  T. Meissner d63dfe6b4a Update uart_reg to full reg file implementation 3 years ago
  T. Meissner 8cf0e6185c blink & uart_reg designs are working now 3 years ago
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 3 years ago
  T. Meissner d57f683506 Adapt sim to updated RTL 3 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 3 years ago