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gatemate_experiments
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2 Commits (3ae59c3b5c723e86893c426333ca42b6a01abc2d)

Author SHA1 Message Date
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago