2 Commits (b2e9cf51553667c780427fe36b21b6c1642670a6)

Author SHA1 Message Date
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
  T. Meissner 6cffeef4a5 Rename components.vhd to rtl_components.vhd 2 years ago
  T. Meissner b8d8b791dc Initial commit 2 years ago