tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
40 Commits
2 Branches
209 KiB
Tree: b8d7ecd701
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'b8d7ecd701'
${ noResults }
Commit Graph

2 Commits (b8d7ecd70125cd23d4b374465b0e7d73db07a5b6)

Author SHA1 Message Date
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago