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gatemate_experiments
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3 Commits (dfd0a5968e0e2645b94ff532640bfbde894f4f61)

Author SHA1 Message Date
  T. Meissner 0df7a047be Add uart_trng design 3 years ago
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 3 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 3 years ago