Add comments with some hints to yosys & p_r options and their effects

neorv32_aes/rtl/neorv32_aes.vhd

@@ -51,9 +51,9 @@ entity neorv32_aes is
     -- LED outputs
     led_n_o   : out std_logic_vector(7 downto 0);
     -- UART0
---    uart_rx_i : in  std_logic;  -- PMODA IO
---    uart_tx_o : out std_logic   -- PMODA IO
-    debug_o : out std_logic_vector(15 downto 0)
+    uart_rx_i : in  std_logic;  -- PMODA IO
+    uart_tx_o : out std_logic;  -- PMODA IO
+    debug_o   : out std_logic_vector(15 downto 0)
   );
 end entity;
 
@@ -140,9 +140,8 @@ begin
     -- Processor peripherals --
     IO_GPIO_EN                   => true,      -- implement general purpose input/output port unit (GPIO)?
     IO_MTIME_EN                  => true,      -- implement machine system timer (MTIME)?
-    IO_UART0_EN                  => false,     -- implement primary universal asynchronous receiver/transmitter (UART0)?
-    IO_CFS_EN                    => false,     -- implement custom functions subsystem (CFS)?
-    IO_AES_EN                    => true       -- implement AES(128) custom function?
+    IO_UART0_EN                  => true,     -- implement primary universal asynchronous receiver/transmitter (UART0)?
+    IO_CFS_EN                    => true       -- implement custom functions subsystem (CFS, AES-CTR)?
   )
   port map (
     -- Global control --
@@ -151,10 +150,8 @@ begin
 	  -- GPIO
     gpio_o  => s_con_gpio,
     -- primary UART0
-    uart0_txd_o => open,  -- uart_tx_o,
-    uart0_rxd_i => '1',  -- uart_rx_i,
-    -- debug
-    debug_o => s_debug
+    uart0_txd_o => uart_tx_o,
+    uart0_rxd_i => uart_rx_i
   );
 
   debug_o <= s_debug(15 downto 0);

uart_aes/rtl/uart_aes.vhd

@@ -1,8 +1,8 @@
--- This design implements a register file which can
+-- This design implements a AES-CTR unit which which can
 -- be accessed by an UART with 9600 baud
 --
 -- See into uart_ctrl.vhd for documentation of the protocol
--- used to read / write the register file.
+-- used to read / write the AES-CTR registers.
 
 
 library ieee ;

uart_aes/syn/Makefile

@@ -4,8 +4,6 @@ AES_DIR   := ../../cryptocores/aes/rtl/vhdl
 CRYPTO_SRC := \
   $(AES_DIR)/aes_pkg.vhd \
   $(AES_DIR)/aes_enc.vhd \
-  $(AES_DIR)/aes_dec.vhd \
-  $(AES_DIR)/aes.vhd \
   $(AES_DIR)/../../../ctraes/rtl/vhdl/ctraes.vhd
 
 WORK_FILES  := \
@@ -21,8 +19,15 @@ GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 ICARUSFLAGS := -Wall -Winfloop -g2012 -gspecify -Ttyp
 
 YOSYSPIPE   := -nomx8
-PNRFLAGS    := -om 3 -cCP on
+# yosys -nomx8 option has to be used as GM FPGA hasn't any (working?) MUX8 cells (in contrast to documentation)
+# yosys -retime option causes design AES unit misbehavior (wrong results)
+# yosys -dff option can be used without risk (but leads to 2.5 mhz less fmax)
+
 PNRTOOL     := $(shell which p_r)
+PNRFLAGS    := -om 3 -cCP off
+# p_r +cCP option causes design AES unit misbehavior (wrong results != retime results)
+# p_r +sp option causes design AES unit misbehavior (wrong results != retime results != cCP results)
+# p_r +cCP with +gCP also breaks UART
 
 
 .PHONY: all syn imp prog syn_sim imp_sim