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gatemate_experiments
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51 Commits
2 Branches
209 KiB
VHDL 71.6%
Makefile 13.9%
Verilog 8.7%
C 5.4%
Tcl 0.4%
 
 
 
 
 
Branch: main
blink_with_pll
main
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gatemate_experiments/uart_reg/rtl
History
T. Meissner 5d9943c78f Remove CC_CTRL_END component, use CC_USR_RSTN instead 2 years ago
..
uart_ctrl.vhd Update uart_reg to full reg file implementation 2 years ago
uart_reg.vhd Remove CC_CTRL_END component, use CC_USR_RSTN instead 2 years ago
uart_rx.vhd Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
uart_tx.vhd Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago
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