library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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entity CC_PLL is
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generic (
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REF_CLK : string := "0"; -- reference clk in MHz
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OUT_CLK : string := "0"; -- output clk in MHz
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PERF_MD : string := "UNDEFINED"; -- LOWPOWER, ECONOMY, SPEED (optional, global, setting of Place&Route can be used instead)
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LOW_JITTER : natural := 1; -- 0: disable, 1: enable low jitter mode
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CI_FILTER_CONST : natural := 2; -- optional CI filter constant
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CP_FILTER_CONST : natural := 4 -- optional CP filter constant
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);
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port (
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CLK_REF : in std_logic;
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CLK_FEEDBACK : in std_logic;
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USR_CLK_REF : in std_logic;
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USR_LOCKED_STDY_RST : in std_logic;
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USR_PLL_LOCKED_STDY : out std_logic;
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USR_PLL_LOCKED : out std_logic;
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CLK270 : out std_logic;
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CLK180 : out std_logic;
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CLK0 : out std_logic := '1';
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CLK90 : out std_logic := '0';
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CLK_REF_OUT : out std_logic
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);
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end entity;
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architecture sim of CC_PLL is
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constant c_period_ns : real := (1000.0 / real'value(OUT_CLK));
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constant c_half_period_ns : real := c_period_ns / 2.0;
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begin
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Log : process is
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begin
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report CC_PLL'instance_name & " CC_PLL CLK0 = " & to_string(1000.0/(c_period_ns), 2) & " MHz";
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wait;
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end process;
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CLK0 <= not CLK0 after c_half_period_ns * ns;
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CLK90 <= transport CLK0 after (c_half_period_ns / 2.0) * ns;
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CLK180 <= not CLK0;
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CLK270 <= not CLK90;
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CLK_REF_OUT <= CLK_REF;
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USR_PLL_LOCKED <= '1';
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end architecture;
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library ieee ;
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use ieee.std_logic_1164.all;
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entity CC_CFG_END is
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port (
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CFG_END : out std_logic
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);
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end entity;
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architecture sim of CC_CFG_END is
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begin
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CFG_END <= '1';
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end architecture;
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