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gatemate_experiments
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17 Commits (0e84416a926a4330b82ec93064ff9e86ba1bf09c)
 

Author SHA1 Message Date
  T. Meissner 0e84416a92 Rename uart folder to uart_reg 3 years ago
  T. Meissner 1003634110 Add inital version of uart register test design 3 years ago
  T. Meissner cfa6f88c55 Add simple gatemate primitives simulation components 3 years ago
  T. Meissner 012de1f868 RTL refactoring 3 years ago
  T. Meissner d57f683506 Adapt sim to updated RTL 3 years ago
  T. Meissner 133e25aa3d Let LEDs rotate instead of counting up 3 years ago
  T. Meissner a0fcc51dc8 Add make target to program FPGA 3 years ago
  T. Meissner eb0d52e2d6 Add blink design info and more links to README 3 years ago
  T. Meissner 81be6cfd05 Add CC_CFG_END unit, Use PLL lock & cfg_end for reset 3 years ago
  T. Meissner f28d35d12b Also remove bit file in clean target 3 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 3 years ago
  T. Meissner 95887cb31d Add PLL to blink design 3 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 3 years ago
  T. Meissner a38eedb326 Add license 3 years ago
  T. Meissner eea3893d1c Fix readme 3 years ago
  T. Meissner e60d14ba47 Add readme 3 years ago
  T. Meissner b8d8b791dc Initial commit 3 years ago