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49 lines
1.1 KiB
49 lines
1.1 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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entity tb_blink is
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end entity tb_blink;
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architecture sim of tb_blink is
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signal s_clk : std_logic := '1';
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signal s_rst_n : std_logic := '0';
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signal s_led_n : std_logic_vector(7 downto 0);
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begin
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dut : entity work.blink
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port map (
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clk_i => s_clk,
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rst_n_i => s_rst_n,
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led_n_o => s_led_n
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);
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s_rst_n <= '1' after 120 ns;
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s_clk <= not s_clk after 50 ns;
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-- Let's test one complete rotate of LED output
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TestP : process is
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variable v_led_n : std_logic_vector(s_led_n'range) := x"FE";
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begin
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wait until s_rst_n;
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wait until rising_edge(s_clk);
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for i in 0 to 7 loop
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report "LED: " & to_hstring(s_led_n);
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assert s_led_n = v_led_n
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report "LED error, got 0x" & to_hstring(s_led_n) & ", expected 0x" & to_hstring(v_led_n)
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severity failure;
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wait until s_led_n'event;
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v_led_n := v_led_n(6 downto 0) & v_led_n(7);
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end loop;
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report "Simulation finished :-)";
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stop(0);
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end process;
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end architecture;
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