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gatemate_experiments
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209 KiB
VHDL
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Makefile
13.9%
Verilog
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Tcl
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gatemate_experiments
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uart_reg
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T. Meissner
6b1b376932
Use speed instead of moderate FPGA speed grade
2 years ago
..
Makefile
Use speed instead of moderate FPGA speed grade
2 years ago
tb_uart_reg.v
Use random stimuli in uart_loop testbench
2 years ago
uart_reg.ccf
Add uart_loop design to test gatemate fifo & ram primitives
2 years ago