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gatemate_experiments/uart_trng/rtl
T. Meissner 6b1b376932 Use speed instead of moderate FPGA speed grade 2 years ago
..
firo.vhd Remove unneeded synthesis attributes for ring oscillator 2 years ago
firo_ctrl.vhd Remove unneeded synthesis attributes for ring oscillator 2 years ago
uart_trng.vhd Use speed instead of moderate FPGA speed grade 2 years ago
uart_tx.vhd Add uart_trng design 2 years ago