tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
44 Commits
2 Branches
209 KiB
 
 
 
 
 
Tree: bf6508d941
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'bf6508d941'
${ noResults }
gatemate_experiments/neorv32_aes/syn
T. Meissner f8ba0b17c2 Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
..
Makefile Update neorv32_aes top level; Add some iverilog options 2 years ago
neorv32_aes.ccf Update neorv32_aes top level; Add some iverilog options 2 years ago
tb_neorv32_aes.v Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago