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gatemate_experiments/neorv32_aes
T. Meissner f8ba0b17c2 Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
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rtl Update neorv32_aes top level; Add some iverilog options 2 years ago
sim Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
syn Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago