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28 lines
682 B
28 lines
682 B
DESIGN := risc_v
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DESIGN_SRC := risc_v_pkg.vhd risc_v.vhd
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TESTBENCH := tb_${DESIGN}
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DEFAULT: sim
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${TESTBENCH} : ${DESIGN_SRC} ${TESTBENCH}.vhd
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ghdl -a --std=08 ${DESIGN_SRC} ${TESTBENCH}.vhd
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ghdl -e --std=08 ${TESTBENCH}
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.PHONY: sim
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sim: ${TESTBENCH}.ghw
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${TESTBENCH}.ghw: ${TESTBENCH}
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ghdl -r --std=08 ${TESTBENCH} --ieee-asserts=disable-at-0 --vcd=${TESTBENCH}.vcd --wave=$@
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.PHONY: syn
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syn: $(DESIGN).json
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$(DESIGN).o: $(DESIGN_SRC)
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ghdl -a --std=08 $(DESIGN_SRC)
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$(DESIGN).json: $(DESIGN).o
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yosys -m ghdl -p 'ghdl --std=08 --no-formal ${DESIGN}; synth_ice40 -json $@'
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.PHONY: clean
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clean:
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rm -f ${TESTBENCH} ${TESTBENCH}.ghw ${TESTBENCH}.vcd work* *.o *.json
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