libvhdl

Commit Graph

Author	SHA1	Message	Date
T. Meissner	4086876e14	Add assert for WB reset; add coverage of Local write/read	9 years ago
T. Meissner	c1005badfc	Add PSL assertions to check initiating of WishBone write/read transfer WB_WRITE & WB_READ check that a write/read transfer is started on the WishBone bus if requested on the local port of the WishBoneMasterE unit at the adequate time.	9 years ago
T. Meissner	6659dbbe31	Fix PSL assertions for local wen and local ren The second logical implication was made the whole property holding when the part after the 1st implication didn't hold. So, the 2nd implication is replaced by an and in combination with the next operator. Now the property fails when one of the two and'ed parts after the implication fails.	9 years ago
T. Meissner	021bab3762	Add PSL assertions to check WishBone & Local IF Various new PSL assertions to check ports during Wishbone write & read transfer and reset state	9 years ago
T. Meissner	f0e490142e	moved register write into ADDRESS state, decreasing the write to one cycle only	10 years ago
T. Meissner	285a25132e	react to slave ack in ADDRESS state	10 years ago
T. Meissner	7d60f0ae1b	add simple wishbone master and slave with support of classic single write and read as specified in the wishbone spec b4; add unit tests for wishbone m,aster & slave	10 years ago
T. Meissner	c221b65074	ste is now generated combinatoral in parallel to the fsm	10 years ago
T. Meissner	5c06158fac	add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa	10 years ago
T. Meissner	034b10cdc9	change G_SCLK_DIVIDER range start to 6 (lowest working divider value) and adapt assertion to new range	10 years ago
T. Meissner	5dd42b80a2	add synthesizable and configurable SPI master component and enhance unit test	10 years ago
T. Meissner	dc24fc93b1	fixed reset initialisation of s_sclk_d	10 years ago
T. Meissner	502aec376a	replaced direct read from async SpiMosi_i input by read from registered a_mosi	10 years ago
T. Meissner	308e33cd0c	synthesis don't like the std_logic'val(int) construct, change to if/else instead	10 years ago
T. Meissner	c9fc7388c9	add synthesizable configurable SPI slave component and unit test	10 years ago
T. Meissner	ac5925c717	add synthesizable configurable SPI slave component and unit test	10 years ago

16 Commits (4d5b2d2464ebb942c198cd587549cf2936f31196)