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Library of reusable VHDL components
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libvhdl/syn
T. Meissner 69c4bc5388 Add UART receive component & UART testbench 4 years ago
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SpiMasterE.vhd ste is now generated combinatoral in parallel to the fsm 10 years ago
SpiSlaveE.vhd add generic G_DATA_DIR to set if we want transfer from LSB to MSB ore vice versa 10 years ago
UartRx.vhd Add UART receive component & UART testbench 4 years ago
UartTx.vhd Add parity bit implementation 4 years ago
WishBoneCheckerE.vhd New Wishbone checks; Fix illegal PSL property 6 years ago
WishBoneMasterE.vhd Add bmc mode; integrate simulation PSL checks 5 years ago
WishBoneP.vhd Add bmc mode; integrate simulation PSL checks 5 years ago
WishBoneSlaveE.vhd Add bmc mode; integrate simulation PSL checks 5 years ago