Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. package pkg is
  4. component sequencer is
  5. generic (
  6. seq : string
  7. );
  8. port (
  9. clk : in std_logic;
  10. data : out std_logic
  11. );
  12. end component sequencer;
  13. end package pkg;